Please help i am not sure if the answer is $1$ bit or $8$bits, please also explain why

Question $9$

A module called dflipflop is defined as below:

entity dflipflop is

generic $($G$\_$DATA$\_$WIDTH : INTEGER :$=32)$;

Port $($ CLK : in std$\_$logic;

rst$\_$n : in STD$\_$LOGIC;

D : in std$\_$logic$\_$vector $($G$\_$DATA$\_$WIDTH$-1$ downto $0)$;

Q : out std$\_$logic$\_$vector $($G$\_$DATA$\_$WIDTH$-1$ downto $0))$;

end dflipflop;

architecture Behavioral of dflipflop is

begin

dff: process $($clk$,$rst$\_$n$)$

begin

if $($rst$\_$n $=\text{'}0\text{'})$ then

Q others $=>\text{'}0\text{'})$;

elsif rising$\_$edge$($clk$)$ then

Q D;

end if;

end process dff;

end Behavioral;

The dflipflop module is instantiated in another module as below. Given that signals CLK$,$ rst$\_$n$,$ D$1$ and

data$\_$in are correctly defined elsewhere, what is the data width that is actually implemented:

dff$1$ : dflipflop

generic map $($G$\_$DATA$\_$WIDTH $=>8)$

port map$($

CLK $=>$ CLK$,$

rst$\_$n $=>$ rst$\_$n$,$

Q $=>$ D$1,$

D $=>$ data$\_$in

;

$1$bit

$8$ bits

$16$ bits

$32$ bits