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The state diagram of figure 3 shows the counting sequence in binary of a 3-bit synchronous counter. Build the counter by using positive triggered JK flip-flops. Unused states are taken as don't care. Design a 3-bit synchronous counter using negative-triggered JK flip-flops that counts as follows: 6,5,1,7,2,4,6 Unused states are taken as don't care. 1)Design the circuit in by using T flip-flops