Please help me run the following verilog code and its test bench. Please show your output. Thank you so much!

module Gray_Binary(

input w,x,y,z,

output a,b,c,d

);

assign a = w;

assign b = w^x;

assign c = w^x^y;

assign d = w^x^y^z;

endmodule

Write the Verilog test bench code.

module Test_Gray_Binary;

// Inputs

reg w;

reg x;

reg y;

reg z;

// Outputs

wire a;

wire b;

wire c;

wire d;

// Instantiate the Unit Under Test (UUT)

Gray_Binary uut (

.w(w),

.x(x),

.y(y),

.z(z),

.a(a),

.b(b),

.c(c),

.d(d)

);

initial begin

// Initialize Inputs

w = 0; x = 0; y = 0; z = 0; #10;

w = 0; x = 0; y = 0; z = 1; #10;

w = 0; x = 0; y = 1; z = 0; #10;

w = 0; x = 0; y = 1; z = 1; #10;

w = 0; x = 1; y = 0; z = 0; #10;

w = 0; x = 1; y = 0; z = 1; #10;

w = 0; x = 1; y = 1; z = 0; #10;

w = 0; x = 1; y = 1; z = 1; #10;

w = 1; x = 0; y = 0; z = 0; #10;

w = 1; x = 0; y = 0; z = 1; #10;

w = 1; x = 0; y = 1; z = 0; #10;

w = 1; x = 0; y = 1; z = 1; #10;

w = 1; x = 1; y = 0; z = 0; #10;

w = 1; x = 1; y = 0; z = 1; #10;

w = 1; x = 1; y = 1; z = 0; #10;

w = 1; x = 1; y = 1; z = 1; #10;

end

endmodule