Please, I need help on this question.

Given the sequence of the actual taken (T)/not taken (N) outcomes of a particular branch:

N, T, N, T, N, T, N, N, N, N.

a) What is the misprediction rate if a one-bit history dynamic branch predictor is used to

predict these 10 branch instances? Assume the initial state is Not Taken.

b) What is the misprediction rate if a two-bit saturation counter branch predictor is used?

Assume the initial instate is weakly not taken.

c) Four pipelined MIPS processors differ from each other only in the way branch is handled.

Assume branch decision and target address are available at the end of the ID stage.

P1: Stall until branch target is clear; branch penalty is 3 cycles.

P2: Predict branch Not Taken; branch penalty is 1 cycle.

P3: Predict branch Taken; branch penalty is 1 cycle.

P4: Delayed Branch; branch penalty is 0.5 cycle.

Assume 4% of unconditional branch, 6% of conditional branch-untaken, and 10% of

conditional branch-taken for a benchmark program. Compute the average CPI (clock

cycles per instruction). Also assume that the ideal CPI is 1.0.