please implement these drawings in logisim. Thanks

4-bit pavallel registor design. I have designed with the Paralle in Paralled aul When R/w=1 the PIPO shift registar will be in read mode. If we set R/w lines equal to ground then the PIpo shift register will be write mode. The above PIPO Shift register can hold 4-bit data at a time. Let ys assume A and B has 4 -bit of data and the ALU wiM give out of at max 4-bit So that can be hold by the c registor watich is of 4-bit. A-bit Reg A is piepo so that it can controlled by R/ line 4-bit Rey B alyo a PIPo sothat it can also controled by R/w his T0 hold the outpat of ALV C Register PIP with R/=1. 4-bit pavallel registor design. I have designed with the Paralle in Paralled aul When R/w=1 the PIPO shift registar will be in read mode. If we set R/w lines equal to ground then the PIpo shift register will be write mode. The above PIPO Shift register can hold 4-bit data at a time. Let ys assume A and B has 4 -bit of data and the ALU wiM give out of at max 4-bit So that can be hold by the c registor watich is of 4-bit. A-bit Reg A is piepo so that it can controlled by R/ line 4-bit Rey B alyo a PIPo sothat it can also controled by R/w his T0 hold the outpat of ALV C Register PIP with R/=1