please make codes for these and show all work.

P2. Create a VHDL file Launch Vivado 2018.3 and follow the instructions in EGR270 VHDL - combinational circuit - Vivado 2018.3. Filename: Lab3INITIALS_SRC Modify comments at beginning of the VHDL program (name, course, description, etc) P3. Create the VHDL design Create Circuit \#1 in VHDL. Use the same signal letters, but lower case to match our naming convention. Synthesize your VHDL code. Correct errors and re-synthesize as necessary. Include the code for the entity section. Identify and include only the entity code here. Include the code for the architecture section. Identify and include only the architecture code here. P4. Create a testbench Create a testbench to test the output for all input combinations, using 10 ns intervals. Filename: Lab3INITIALS_TB Modify comments at beginning of the VHDL program (name, course, description, etc) Correct errors and recheck as necessary. Include the code for the stimulus section. Identify and include only the stimulus code here