Please provide MIPS code for this question.

1. Consider the following multi-cycle data path (which uses buses instead of some direct paths) Consider the following Machine Language instruction, and its associated meaning addi rt,rs, imned n add the contents of register numbered rs and sign-exten lwi rt, offset (rs) \# imed and place the result in register numbered " sign extended offset + contents of register rs \# Then, increment the contents of register rs by 4 The encoding of these instructions is given below. Write a sequence of RTL (ala MAL) instructions to fetch aud execute the above instructions on the given data path. Assume that register pe bas the address of the addi instruction; mala: sitre that after the excation of lwi instruetion, pe contains the address of the next instruction. Feel free to write comments for your RTL instractions. Example RTL instructions: PCMDR Copy contents of PC to MDH (through the bus) MDRMAR * Copy contents of MDR to MAR (through direct path) M[MAR] MDR Copy conente of menory location whose address is in MAR to MDR