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Part B - 2's Complement 4-Bit Saturator Figure 1 shows a circuit that was described in the November 2001 issue of NASA Tech Briefs Study the circuit to understand how it works. The circuit will take a 6-bit two's complement number with a signed value between -32 and +31 and convert it to a 4-bit two's complement number with a signed value between -8 and +7. Negative input values less than -8 will be saturated at-8. Positive input values greater than +7 will be saturated at +7. Figure 1 Figure 1. Multiplexer A Output Input YO Y1 Y2 Y3 XO X2 2 Input Lines X3 3 C1 X4 CO X5 5 Most Significant Bit This Circuit Generates a Saturated Four-Bit Output in response to a six-bit input. The exclusive-OR gates examine the num- ber of high-order bits to be eliminated, plus one, to determine whether they are already all alike. If so, the input quantity is deemed to be within the saturation range, and is itself gated through the multiplexer. If not, a maximum positive or neg- ative quantity is derived from the sign bit and gated through the multiplexer. This circuit implements 2's-complement en- coding of negative numbers