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Winter 202 PROBLEM 4 (26 PTS) a) Complete the timing diagram of the following circuit: (5 pts) 1 a NI 1 1 b I a 1 . 1 c . De 1 1 1 1 1 1 b) Complete the timing diagram of the logic circuit whose VHDL description is shown below: (7 pts) library ieee; use ieee.std logic 1164.all: a D 13 LE entity circ is port ( a, b, c: in std logic; f: out std_logic); end circ; 1 b 0 1 1 architecture struct of circ is signal x, y: std logic; 1 1 . . begin fde y and (not b); x 4 not (a) Kor y