please show brief explanation

7. Consider the following MIPS code: srl $t0,$s2, 29 sll $s1, $s2,3 or $81, $81, $to The above code does the following A. rotate left $s2 by 3 bits and store the result in $s1 B. rotate left $s2 by 29 bits and store the result in $s1 C. rotate right $s2 by 29 bits and store the result in $sl D. rotate right $s2 by 3 bits and store the result in $s1 8. In a single-cycle processor, if ALUScr has a stuck-at-1 fault (i.e., the signal is always 1), then: A. All R-type instructions will not work. B. All 1-type instructions will not work. c. All branching instructions such as BEQ and BNE will not work. D. R-type instructions with a second source register rt, such as ADD and SUB, will not work. 9. In a single-cycle processor, if ALUOP1:0 has a stuck-at-00 fault (i.e., the signal is always 00), then A. All R-type instructions will work properly. B. All R-type instructions with a second source register rt, such as ADD and SUB, will not work. C. I-type instructions such as LW and SW will work properly. D. Both (A) and (C) 10. Consider two different implementations, M1 and M2, of the same instruction set. Mi is a single-cycle implementation with a clock rate of 100 MHz and M2 is a multicycle version which operates with a 450 MHz clock. Assume that the multicycle datapath discussed in class is used for M2 to determine the number of clock cycles for each instruction type. Given a program with the 20% loads, 10% stores, 50% ALU operations, 20% jumps and branches, which of the following is true: A. M2 is 1.125 times faster than Mi. B. Mi is 1.125 times faster than M2. C. M1 and M2 will have the same execution time for the given program. D. None of the above