Please show me how to do this with steps and explanation. Thank you!

6 - Complete the pipeline diagram for the sequence of code in the following table from cycle 1 to cycle 11 Assume the following: The processor has a 5-stage pipeline. All forwarding paths are available .The branch instruction is resolved in the ID stage .The branch instruction is not delayed. Instruction fetching or data memory access takes only one cycle. The loop is performed many times and 16 in the table is taken. Cycle 4 6 78 9 10 11 I1: LW $1, ($8) I2: LW $2, ($9) I3: SUB $3,$1,$2 I4: ADD $4,$3,$4 I5: ADDI $8,$8,4 I6: BNE $8,$7,11 I7: ADD $1,$0,$0 I1: LW $1, ($8) IF | ID | EX | ME | WB IF ID EXMEWB Fill in the following blanks with integers. The number of cycles required for each iteration is In each iteration, the number of stall cycles due to data hazards is In each iteration, the number of stall cycles due to control hazards is Instruction scheduling can reduce the number of cycles required for each iteration to 6 - Complete the pipeline diagram for the sequence of code in the following table from cycle 1 to cycle 11 Assume the following: The processor has a 5-stage pipeline. All forwarding paths are available .The branch instruction is resolved in the ID stage .The branch instruction is not delayed. Instruction fetching or data memory access takes only one cycle. The loop is performed many times and 16 in the table is taken. Cycle 4 6 78 9 10 11 I1: LW $1, ($8) I2: LW $2, ($9) I3: SUB $3,$1,$2 I4: ADD $4,$3,$4 I5: ADDI $8,$8,4 I6: BNE $8,$7,11 I7: ADD $1,$0,$0 I1: LW $1, ($8) IF | ID | EX | ME | WB IF ID EXMEWB Fill in the following blanks with integers. The number of cycles required for each iteration is In each iteration, the number of stall cycles due to data hazards is In each iteration, the number of stall cycles due to control hazards is Instruction scheduling can reduce the number of cycles required for each iteration to