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A reduced-xor function works by applying xor operations over all bits of an input signal. For example, let a7a6a5a4a3a2a1a0 be an 8-bit signal. The reduced-xor of this signal is

y= a7 xor a6 xor a5 xor a4 xor a3 xor a2 xor a1 xor a0

Since this function returns 1 if there are odd number of 1s in its input, it can be used to determine the odd parity of the input signal.

(a) Show conceptual design of reduced xor using 2 input xor gates so that the propagation delay of the circuit (critical path) is equal to propagation delay through 3 xor gates. Assume that there are D flip-flops at the input and ad the output of the circuit.

(b) If the propagation delay through xor gate is 0.5ns and Tcq=0.8ns and Tsetup=0.2 ns compute the maximum clock frequency of the circuit.