PLEASE SHOW THE CODE Verilog or VHD code

Design and construct a synthesizable Finite State Machine and Datapath which computes the greatest common denominator (GCD) of two numbers ( two 4-bit) numbers and output the binary value of the greatest common divisor of those two numbers.

Your design will consist of two components - the controller and the datapath. The controller is to be a pure FSM. The datapath operates based on signals generated by the controller FSM - it should have no independent controlling logic. ((datapath must be constructed structurally))

Use the GCD algorithm to help you with the code

CA 35-bits L-bits whil lol all 25) C Loran Comp Select delte 3-bi -1 2 shif Select de bit Adder 5 ad