Question: Please solve i have just 18 min i will give u like if you solve correctly ( digital system design course ) Question 1 timescale

Please solve i have just 18 min i will give u like if you solve correctly (digital system design course)

Question 1 "timescale 1 ne / ips module TEST_gate; reg[1:0ja, b: initial begin a-2b00: #10 b=2'b11: $10 a-2'bll: end initial begin b2'b00#40 a-2b01: end initial #60 Stinis endmodule Which of the following correctly represents the values of "a" and "b" at the 40th nanosecond according to the above verilog code

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