please solve q3 only i have the answer for q1 and q2 i need the answer for q3

3. Build a new module which takes X as an input while the output Y = 2X^2 + x^3 + X, using the ROM modules you built in parts 1 and 2. $iverilog -o main *. ..V $vvp main Address = 1 , 2X^2+X^3+X= Address = 2 , 2X^2+X^3+X= 4 18 able2 X^2 X^3 x X^2 X^3 1 1 1 9 81 729 N 4 8 10 100 1000 3 9 27 11 121 1331 4 16 64 12 144 1782 5 25 125 13 169 2197 6 36 216 14 196 2744 7 7 49 343 15 225 3375 8 00 64 512 You have to print screenshot for the 3 codes as described below 1.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^2. $iverilog -o main *.v $vvp main Address = 5 OUT= 6 OUT= 25 36 Address = 2.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^3. $vvp main Address = Address = Address = 1 OUT= 2 OUT= 4 OUT= -100 8 64