please use c$++$ for this

Cache Simulator $(70$ points$)$:

Write a program to simulate caches of different configurations. Make the following

assumptions about all the caches we simulate.

$1.$ The replacement strategy is LRU $($Least Recently Used$),$ if needed.

$2.$ The cache starts empty.

$3.$ In write$-$through, the processor stalls until the data is written to the memory

before proceeding. That is$,$ the memory and cache are always consistent.

The basic cache is

$$ Cache Size: $2048$ Bytes

$$ Block Size: $2$ words, or $8$ bytes

$$ Cache Placement Type: direct mapped

$$ Write Policy: write back

You must simulate the basic cache, as well as the configurations in one of the

following categories. For example, if you choose the category of cache size, then

you will need to simulate four different configurations: $(1)8192$ bytes cache size,

$2$ words block size, direct mapped, and write back; $(2)16384$ bytes cache size, $2$

words block size, direct mapped, and write back; $(3)32768$ bytes cache size, $2$

words block size, direct mapped, and write back; $(4)65536$ bytes cache size, $2$

words block size, direct mapped, and write back.

Cache Size $($in bytes$)$:

$1.8,192$

$2.16,384$

$3.32,768$

$4.65,536$

Block Size $($in Words or $[$Bytes$])$:

$1.2[8]$

$2.4[16]$

$3.8[32]$

$4.32[128]$

$2$

Cache Placement Type:

$1.$ Fully associative

$2.4-$way set associative

$3.2-$way set associative

$4.$ Direct Mapped

Write Policy:

$1.$ Write back

$2.$ Write through

Note that you have to write only one program that simulates all cache

configurations, one after the other. You might want to use the fact that a direct$-$

mapped cache is also a $1-$way set associative cache.

Input File Format: We will use trace files to simulate our cache configurations.

Each trace file is a sequence of memory accesses, one on each line, with the

format:

read addressHex OR

write addressHex

where address is a $32-$bit address given in hex. An example file, example.trace

is provided on canvas and can be viewed in any text editor.

Output File Format: Your program should summarize the result of simulation for

each cache configuration for a given trace file. The output must be a text file called

test.result.

Each line represents result for one specific cache configuration and is formatted

as follows:

$10248$ FA WB $0\mathrm{.}911024512128$

The above numbers represent the following:

$1.$ Cache size $($in Bytes$)$

$2.$ Block size $($in Bytes$)$

$3.$ Mapping type $($DM$,2$W$,4$W$,$ and FA for direct$-$mapped, $2-$way and $4-$way

set associative, and fully$-$associative caches respectively$)$

$4.$ Write policy $($WB$,$ WT$)$

$5.$ Hit rate $($two decimal points$)$

$6.$ Total Bytes transferred from memory to the cache

$7.$ Total Bytes transferred from cache to memory

$8.$ Number of blocks within each block set

$3$

An example file is provided under the assignment link. You can view this using

Notepad$++$ or other text editors.

Execution Format: Your program should, by default, be able to read in the input

trace file named $$test$.$trace$$ and produce at the end an output file named

$$test$.$result$.$ Name your main executable $($in case of C$/$C$++/$Python$)$ as $$simulate$.$