#pragma config POSCMOD = EC, FPLLIDIV = DIV_2, FPLLMUL = MUL_20, FPLLODIV = DIV_1 #pragma config FPBDIV = DIV_8 Using the pragma directives above and using an 8 MHz clock into the PLL and a 256:1 prescaler for Timer 1 answer the following: System clock frequency: ______ Peripheral Bus clock frequency: ______ Maximum time in seconds the Core Timer can be used to measure: _______ Maximum time in seconds that peripheral Timer1 can be used to measure: _________