Pre-lab 5 Problem 1 Study all three VHDL codes (code (1), (2) and (3)) and answer the questions 1 and 2. (1) Component 1 - NAND gate VHDL file library ieee; use ieee.std_logic_1164.all; entity NAND_ent is port( x: in std_logic; y: in std_logic; Z: out std_logic); end NAND ent; architecture behav2 of NAND ent is begin Z