Pre-lab Activity [3 marks]. Create a new Quartus Il project as a Verilog module for the 2's compliment circuit called Twos_comp. Use switches SW[3:0] to define the input number, where SW[3] is the sign bit. Use the wire M to represent the inverted input and use LEDG[3:0] as the 2's compliment output. module Twos_comp (SW, LEDG, LEDR); input [3:0] SW; output [3:0] LEDR; output [3:0] LEDG; wire [3:0] M; assign LEDR = SW; assign M = %% Insert the logic expression here %%; assign LEDG = %% Insert the logic expression here %%; endmodule Compile the project and simulate it if you can to confirm the results. Hand in a copy of the code to the Lab TA at the start of the lab