Priority Arbiter is a circuit which accepts multiple input and outputs the index of the input

with highest value. This circuit is used in networking equipment where the next packet to

send is selected according to a quality$-$of$-$service $($QoS$)$ policy that gives each packet a

score. The packet with the highest score is sent first.

Figure $2$ show a block diagram of Priority Arbiter Circuit with four inputs and one

output. As example to the Arbiter's function, suppose the four inputs are $21,30,45,$ and

$18.$ The Arbiter will output $2$ because input $2$ has the highest value, $45.$ In the event of a

tie, the circuit outputs the lowest index that has the highest value. If the four inputs are $16,$

$25,20,25,$ the Arbiter will output $1$ because of the two inputs $(1$ and $3)$ with the high

value of $25,$ input $1$ has the lowest index.

Based on the block diagram shown in Figure $2,$ construct the Priority Arbiter Circuit

using Verilog HDL$.$