Problem $02$: $(35$ points$)$ This exercise is intended to help you understand the cost$/$complexity$/$performance trade$-$offs of forwarding in a pipelined processor. Problems in this exercise refer to pipelined datapaths from Figure $4\mathrm{.}45($textbook$).$

These problems assume that, of all the instructions executed in a processor, the following fraction of these instructions have a particular type of RAW data dependence.

The type of RAW data dependence is identified by the stage that produces the result $($EX or MEM$)$ and the instruction that consumes the result $(1$st instruction that follows the one that produces the result, $2$nd instruction that follows, or both$).$ We assume that the register write is done in the first half of the clock cycle and that register reads are done in the second half of the cycle, so $"$EX to $3$rd$"$ and "MEM to $3$rd$"$ dependences are not counted because they cannot result in data hazards. Also, assume that the CPI of the processor is $1$ if there are no data hazards.

Assume the following latencies for individual pipeline stages. For the EX stage, latencies are given separately for a processor without forwarding and for a processor with different kinds of forwarding.

a$)$ If we use no forwarding, what fraction of cycles are we stalling due to data hazards?

b$)$ If we use full forwarding $($forward all results that can be forwarded$),$ what fraction of cycles are we staling due to data hazards?

c$)$ Let us assume that we cannot afford to have three$-$input muxes that are needed for full forwarding. We have to decide if it is better to forward only from the EX$/$MEM pipeline register $($next$-$cycle forwarding$)$ or only from the MEM$/$WB pipeline register $($two$-$cycle forwarding$).$ Which of the two options results in fewer data stall cycles?

d$)$ For the given hazard probabilities and pipeline stage latencies, what is the speedup achieved by adding full forwarding to a pipeline that had no forwarding?

e$)$ What would be the additional speedup $($relative to a processor with forwarding$)$ if we added time$-$travel forwarding that eliminates all data hazards? Assume that the

yet$-$to$-$be$-$invented time$-$travel circuitry adds $100$ ps to the latency of the fullforwarding EX stage.

f$)$ Repeat c$)$ but this time determine which of the two options results in shorter time per instruction.