Problem $1(30$ points$)$ Consider a word addressing architecture with $12-$bit memory

addresses.

$(1)$ Which bits of the address would be used in the tag, index and offset in a direct$-$

mapped cache with $641-$word blocks?

$(2)$ Which bits of the address would be used in the tag, index and offset in a direct$-$

mapped cache with $322-$word blocks?

$(3)$ Which bits of the address would be used in the tag, index and offset in a direct$-$

mapped cache with $164-$word blocks?

$1$

$(4)$ We now double the total capacity of the memory and make it $2-$way set associative

with $64$ sets with two $1-$word entries each. Which bits of the address would be used

in the tag, index and offset? Compare this with the first question above.

$(5)$ Doubling the total capacity of the memory one more time makes it $4-$way set asso$-$

ciative with $64$ sets with four $1-$word entries each. Which bits of the address would

be used in the tag, index and offset?