Problem $1(60$ points$).$ Consider the complete MIPS pipelined datapath that we have learned, which is capable of detecting hazards, using forwarding paths to resolve hazards, and computing branch outcomes in the ID stage. Specifically, for this problem assume there are forwarding paths, forwarding logic, and hazard detection logic that enables forwarding from the EX$/$MEM and MEM$/$WB pipeline registers to the ALU inputs and the ID stage $($for determining branch outcomes$).$ Also assume that branch prediction and delay slots are not used in this problem. An example of the datapath is given in Figure $1,$ noting that not all hardware is necessarily shown in the diagram. Figure $2$: Sample pipeline execution diagram. Draw the pipeline execution diagram for the two sequences of instructions given below when

executed in the pipelined datapath described above. For sequence A assume the branch instruction is not taken, and for sequence B assume the branch instruction is taken. Your pipeline execution diagram should clearly indicate the forwarding paths that may be used and clearly mark a bubble $($i$.$e$.,$ stalled instruction$).$ An example of a pipeline execution diagram is given in Figure $2.$ You must draw a similar diagram but for the following sequences of instructions:

Sequence $($A$)$

add $t$0,$ $t$1,$ $t$2$

ori $t$1,$ $t$0,0$xF

lw t$1,0($t$1)$

beq $t$0,$ $t$1,$ LABEL

sw t$1,0($t$0)$

Sequence $($B$)$

sub $t$0,$ $t$1,$ $t$2$

and $t$0,$ $t$0,$ $t$2$

add $t$1,$ $t$0,$ $t$2$

beq $t$0,$ $t$1,$ LABEL

lw t$2,0($t$3)$

LABEL: $1$w t$3,0($t$4)$ Problem $1(60$ points$).$ Consider the complete MIPS pipelined datapath that we have learned, which is capable of detecting hazards, using forwarding paths to resolve hazards, and computing branch outcomes in the ID stage. Specifically, for this problem assume there are forwarding paths, forwarding logic, and hazard detection logic that enables forwarding from the EX$/$MEM and MEM$/$WB pipeline registers to the ALU inputs and the ID stage $($for determining branch outcomes$).$ Also assume that branch prediction and delay slots are not used in this problem. An example of the datapath is given in Figure $1,$ noting that not all hardware is necessarily shown in the diagram.

Figure $1$: Pipelined datapath depicting forwarding and branch computation in the ID stage.

Figure $2$: Sample pipeline execution diagram.

Draw the pipeline execution diagram for the two sequences of instructions given below when executed in the pipelined datapath described above. For sequence A assume the branch instruction is not taken, and for sequence B assume the branch instruction is taken. Your pipeline execution diagram should clearly indicate the forwarding paths that may be used and clearly mark a bubble $($i$.$e$.,$ stalled instruction$).$ An example of a pipeline execution diagram is given in Figure $2.$ You must draw a similar diagram but for the following sequences of instructions:

Sequence $($A$)$

$```$

add $t$0,$ $t$1,$ $t$2$

ori $t$1,$ $t$0,0$xF

lw $t$1,0($$t$1)$

beq $t$0,$ $t$1,$ LABEL

sw $t$1,0($$t$0)$

$```$

Sequence $($B$)$

sub $\backslash$$t$0,\backslash$$t$1,\backslash$$t$2$

and $\backslash$$t$0,\backslash$$t$0,\backslash$$t$2$

add $\backslash$$t$1,\backslash$$t$0,\backslash$$t$2$

beq $\backslash$$t$0,\backslash$$t$1,$ LABEL

$1$w $\backslash$$t$2,0(\backslash$$t$3)$

LABEL: $1$w $\backslash$$t$3,0(\backslash$$t$4)$