Problem $1$: $(6$ marks$)$ Design a datapath and control unit

Consider the following diagram: $(2$ marks for each part$)$

rose

Give the values of ALL control signals generated by this instruction below for its basic implementation in the shown MIPS pipelined datapath by completing the Table below. add $$t0,$$$s1,$$$s2$

$\backslash$table$[[$RegDst$,$ALUOp$1,$ALUOp$0,$ALUSrc,Branch,PCSrc$,$MemRead,MemWrite,RegWrite,MemtoReg$],[,,,,,,,,,]]$

Give the values of ALL control signals generated by this instruction below for its basic implementation in the shown MIPS pipelined datapath by completing the Table below. sw $$s1,20($$s$5)$

$\backslash$table$[[$RegDst$,$ALUOp$1,$ALUOp$0,$ALUSrc,Branch,PCSre,MemRead,MemWrite RegWrite MentoReg,$],[,,,,,,,,]]$

Give the values of ALL control signals generated by this instruction below for its basic implementation in the shown MIPS pipelined datapath by completing the Table below. beq $$t0,$$$t1,$ Label

$\backslash$table$[[$RegDst$,$ALUOpl,ALUOp$0,$ALUSro,Branch,PCSro,MemRead,MemWrise,RegWrite,MantoRes$],[-,,-,,,,,,1,]]$

$2$