Problem $1$:

Consider a dual$-$issue CDC $6600-$like processor with $2$ adders, $2$ multiplier$/$division units having the following

latencies:

$2$ cycle for an add.

$11$ cycles for a multiply.

$15$ cycles for a divide.

and the following program segment:

$i_1$:$,R_{1}larr{R}_2+R_3$

$i_2$:$,R_2$larr$\frac{R_1}{R_4}$

$i_3$:$,R_4-R_5+R_6$

$i_4$:$,R_4-R_7***R_8$

$i_5$:$,R_{7}larr{R}_1+R_2$

Assuming all registers are initially free and that $i_1$ is issued at $t_0,$ show the scoreboard at cycle $t_5.$ At what

time will each instruction complete?