Problem $1$

Consider the following arithmetic function: f $=((($A $+$ B$)$ x C$)+$ D$)$ x $($E $+$ F$)$

The following components are available and they have the delays and areas shown below:

Component, Delay, Area

$2-$input adder $,10,50$

$2-$input multiplier $,50,1,00$

Edge$-$triggered register $,3,10$

N$-$input multiplexer $($N being a power of $2$ number$),5,5*$N

a$)$ Assume unlimited resources available and that no pipelining is required, implement the

design for f and show the timing diagram making sure to specify when the output of

each component $($adder and multiplier$)$ will be stable.

b$)$ Implement a fully pipelined circuit for part $($a$)$ and show the timing diagram for $2$ sets

of inputs.

c$)$ Implement a pipelined circuit for part $($a$)$ assuming only $2$ pipeline stages and show the

timing diagram for $2$ sets of inputs.

d$)$ Implement the design for f and show the timing diagram given that:

$$ Only a single multiplier and $2$ adders are available.

$$ No pipelining is required.

e$)$ Implement the design for f and show the timing diagram given that:

$$ Only a single multiplier and a single adder are available.

$$ No pipelining is required.

f$)$ Provide a table summarizing the overall delay and the overall areas for all the design

modifications you performed and comment on the effect of the modification with respect

to timing, number of resources used, area, and throughput $($specifically between parts

$($b$)$ and $($c$)).$ Comment on trade$-$offs if any.

In all parts of this problem, you are to optimize your design as much as possible with

respect to delay but also with respect to the use of registers, multiplexers, and control

signals, but with the delay having the highest priority.

Make sure you clearly show the timing information for all the relevant signals in the design

and when$/$how often outputs are generated $($especially for the pipelined versions$).$ In

addition, you are not allowed to reorder the operations.