Problem $1$: Layout the minimum $2$ input NAND standard cell. Assume power, ground, etc. can be

routed above the standard cells $($i$.$e metal routing does not set size of cell$).$ What are the x and y

dimensions? Home many track library would this cell allow? Use TSMC $0\mathrm{.}25$um deep submicron

design rules found in Module $3$ on UF elearning.

Cell Height $=?$

Cell Width $=?$

Gate

Cell Width from active edge to active edge