Problem 1: Multiple Choice (30 points) For each question below, underline or circle the most appropriate answer . Multilevel cache design is one technique to reduce ) Cache miss penalty (b) Cache miss rate (c) Cache hit time terms of cache coherency "misses", we have true sharing misses and false sharing misse Which one of the statements below is true: (a) Coherency misses increase with increasing cache size only (b) Coherency misses increase with decreasing cache size only (c) Coherency misses increase when we increase the number of processors in the system (d) Coherency misses decrease when we increase the number of processors in the syste The performance of a pipeline processor is typically measured in terms of (a) k- the number of stages in the pipeline (b)-the clock cycle of the stages (c) latency of the pipeline (d) throughput of the pipeline (e) all of the above (f) none of the above Internal forwarding (bypassing) is a technique in pipelines that (a) reduces stalls due to control hazards (b) reduces stalls due to WAR dependencies (c) reduces stalls due to RAW dependencies (d) reduces stalls due to structural hazards (e) all of the above (f) none of the above Because of the memory-processor performance gap, cache performance is (a) less importance in faster processors (b) more importance in faster processors (c) unchanged in importance in faster processors