Problem # $1$: Multiple choice question. $[81$ pt$]$

In the $q,,$ multiple ALUs within a core controlled by the same instruction.

A$.$ Superscalar

B$.$ Multi$-$core

C$.$ SIMD

D$.$ None of the above

$$ exploits ILP within an instruction stream within a core to process different instructions from the same instruction stream.

A$.$ Superscalar

B$.$ Multi$-$core

C$.$ SIMD

D$.$ None of the above

In case $8$ core processor operating at $3GHz,$ and two $16-$wide SIMD ALUs per core, the GFLOPs $($Billion Floating$-$Point Operations per Second$)$ is $q,$ A$.768$

B$.384$

C$.256$

D$.$ None of the above

The portion of power that is burned by transistors when they are inactive due to leakage is $s$ called $q,$ A$.$ Dynamic power

B$.$ Background power

C$.$ Static power

D$.$ None of the above

$q,$ is a cache replacement algorithm used for freeing the memory space for the new data by removing the data in the cache that was accessed for the longest time ago.

A$.$ Least Recently Used $($LRU$)$

B$.$ Least Frequently Used $($LFU$)$

C$.$ First in First out $($FIFO$)$

D$.$ None of the above

Which of the following is an example of the SIMD instruction sets supported by recent $CP{U}_s$ manufactured in Intel and AMD?

A$.$ SSE $($streaming SIMD extensions$)$

B$.$ AVX $($advanced vector extensions$)$

C$.(A+B)$

D$.$ None of the above