Problem $1$

Reconsider the system that you implemented in Project $2$ consisting of the$$transmit$$and$$receive$$modules$.$

In Project $2,$ the register was an ideal device. That is$,$ it had zero propagation delay and zero setup and hold time.

Let's repeat the clock period calculation of Project $2$ with new details about the register's delay characteristics.

Each register has a propagation delay of $10$ ns$,$ a setup time of $4$ ns$,$ and a hold time of $2$ ns$.$

The HC$280$ has a $($worst case$)$ propagation delay of $40$ ns$.$

The counter has a propagation delay of $38$ ns$,$ a setup time of $16$ ns$,$ and a hold time of $0$ ns$.$

The comparator is a $2-$input XNOR gate having a propagation delay of $8$ ns$.$

$$

Flag question: Question $1$

Question $14$ pts

What is the clock$-$to$-$clock critical path time $($in nanoseconds$)$ of the transmit module?

Give your answer as a number only.