Problem 2 a) Consider a non-pipelined machine with 5 stages of lengths 20 ns, 40 ns, 60 ns, 10 ns and 30 ns. Suppose we introduce pipelining on this machine. Assume that when introducing pipelining, the clock adds 4 ns latch. i. What is the clock cycle time on the non-pipelined machine? [1 mark] ii. What is the clock cycle time on the pipelined machine with latch? [1 mark] iii. Calculate the execution time to execute 300 instructions on the non-pipelined machine? Show your work. [2 marks] iv. Calculate the execution time to execute 300 instructions on the pipelined machine? Show your work. [2 marks] v. Calculate the speedup gained? [2 marks] b) Consider a hypothetical 64-bit microprocessor having 64-bit instructions composed of three fields: the first byte contains the opcode, the second two bytes field is an Page 2 of 4 immediate operand field, and the third is for an address field. What is the maximum directly addressable capacity for a byte addressable memory in bytes? [2 marks] [Q2 Total: 10 marks]