Problem $2$:

Consider the following computation loop $x_{i+1}=a{x}_i-b{Y}_i$ which is the inner loop in a numerical

algorithmic process. For numerical convergence, this loop is supposed to run for a large number of iterations.

The constants a and $b$ are initialized in float registers.

Assume the pipeline data dependent latencies between instructions $($WRITE to READ operands$)$ are given

by the following Table. For example, LD F$0,$ O$($R$1)$ and MULTF F$0,$F$0,$F$2$ have a RAW dependency with

latency $($load slot$)1$ slot. Also, the machine uses float arithmetic units $($ADDF and MULTF$)$ which are

pipelined and embedded in the instruction pipeline. You may consider $4-$stage float pipes. Furthermore,

delayed branching is available.

a$)$ Unroll the above loop as many times as necessary to schedule it without any delays, collapsing the

loop overhead instructions.

b$)$ Briefly show the scheduling of the entire loop iterations.

c$)$ Comment if there are other unrollings feasible.