Problem 2. Instruction Flow and Branch Prediction (30 points) Write down all assumptions. If you need more space, attach additional pages to the back, and label accordingly. Please save your work for this problem after you submit your answers. We will build on this assignment as we go through the semester and see alternative processor designs. Introduction This problem investigates the effects of branches and control flow changes on program perfor- mance for a scalar pipeline (to keep the focus on branch prediction). Branch penalties increase as the number of pipeline stages increases between instruction fetch and branch resolution (or condition and target resolution). This effect of pipelined execution drives the need for branch prediction. This problem explores both static branch prediction in Part C (we will see dynamic branch prediction based on this design in a future assignment). For this problem the base machine is a 5-Stage pipeline. The 5-Stage Pipeline without Dynamic Branch Prediction Br. Corr. Address FeeN Instruction Cache Addr Sequential Addr. Calc. Instruction Fetch Instructions Execution Assumptions: unconditional branches execute in the decode stage conditional branches execute in the execute stage Effective address cal- culation is performed in the execute stage All memory access is performed in the mem- ory access stage All necessary forward- ing paths exist The register file is read after write Instruction Decode Execute The fetch address is a choice between the sequential address generation logic and the branch correction logic. If a mispredicted branch is being corrected the correction address is chosen over the sequential address for the next fetch address. Memory Access Write Back Part A: Branch Penalties. [4 points) What are the branch penalties for unconditional and conditional branches? Unconditional Conditional Scanned by CamScanner Problem 2. Instruction Flow and Branch Prediction (30 points) Write down all assumptions. If you need more space, attach additional pages to the back, and label accordingly. Please save your work for this problem after you submit your answers. We will build on this assignment as we go through the semester and see alternative processor designs. Introduction This problem investigates the effects of branches and control flow changes on program perfor- mance for a scalar pipeline (to keep the focus on branch prediction). Branch penalties increase as the number of pipeline stages increases between instruction fetch and branch resolution (or condition and target resolution). This effect of pipelined execution drives the need for branch prediction. This problem explores both static branch prediction in Part C (we will see dynamic branch prediction based on this design in a future assignment). For this problem the base machine is a 5-Stage pipeline. The 5-Stage Pipeline without Dynamic Branch Prediction Br. Corr. Address FeeN Instruction Cache Addr Sequential Addr. Calc. Instruction Fetch Instructions Execution Assumptions: unconditional branches execute in the decode stage conditional branches execute in the execute stage Effective address cal- culation is performed in the execute stage All memory access is performed in the mem- ory access stage All necessary forward- ing paths exist The register file is read after write Instruction Decode Execute The fetch address is a choice between the sequential address generation logic and the branch correction logic. If a mispredicted branch is being corrected the correction address is chosen over the sequential address for the next fetch address. Memory Access Write Back Part A: Branch Penalties. [4 points) What are the branch penalties for unconditional and conditional branches? Unconditional Conditional Scanned by CamScanner