PROBLEM $2.$ Logical effort. $(16$pts$)$

Consider two implementations of an $8-$input AND gate:

$-$ Design A consists of two $4-$input domino AND gates, followed by a $2-$input domino AND. Inverters in domino stages are high$-$skewed, with PMOS transistors being $4$ times wider than NMOS.

$-$ Design B consists of a two dynamic $4-$input NAND gates, followed by a $2-$input high$-$skewed static NOR $($such that PMOS transistors are two times wider than NMOS$).$

You cannot eliminate the foot switch. Assume that the diffusion capacitance at the output node dominates the parasitic gate delay.

Your task is to compare the speed of these two designs. Please show your work and explain your reasons.

a$)(8$pts$)$ Which design is faster if the output capacitance is equal to the input capacitance?