Problem # $2$: Suppose processors P$1$ and P$2$ have private and snoopy caches. Both caches are initially empty. Consider the sequence of memory accesses shown in the table below. Assume three cache blocks $A,B,$ and $C$ do not conflict in the cache. Using the standard MESI write$-$invalidate coherence protocol for a write$-$back cache, fill in the table below with the states of the three cache blocks $($i$.$e$.,$ A$,$ B$,$ and C$)$ in each processor cache and the appropriate action should be taken in both processor caches after each processor memory operation. $[3$pts$]$

Processor memory operation Processor P$1\text{'}$s cache Processor P$2\text{'}$s cache

Initial sate

P$2$: readA

P$1$: read $B$

P$1$: write $C$

P$2$: write A

$P1$:readA

P$2$: write B

P$2$: read B

P$2$: readA

P$2$: write $C$

P$2$: write C

P$2$: read $C$

P$2$: write B

P$1$: write A

P$2$: write A

$P1$:readA

$P2$:readA