Problem 2: Suppose that we can design a cache hierarchy with 1 or more of the following devices Cache Size 32 KB 128 KB 512 KB 2 MB 8 MB Latency (Clock Cycles) Misses Per Thousand Instructions (MPKI) 100 80 50 4 16 Assume that accessing off-chip memory takes 200 clock cycles For the following cache configurations, calculate the average time spent accessing the cache hierarchy. What do you observe about the downsides of a cache hierarchy that is too shallow or too deep? (Here, too shallow means having only a small number of levels and deep means having many levels.) 32 KB L1; 8 MB L2; off-chip memory 32 KB L1; 512 KB L2; 8 MB L3; off-chip memory C. 32 KB L1; 128 KB L2; 2 MB L3; 8 MB L4; off-chip memory