Problem $3$: $(16$ points$)$

Your single$-$cycle processor seems to be executing random instructions. You need to find out why. On the next page is a picture of your datapath $($note that this is somewhat different from the datapath used in class$)$ and the control table is below. You suspect that the controller is broken. You may assume that the datapath modules $($e$.$g$.,$ the ALU, etc.$)$ work correctly.

You may assume the following are correct:

$-$ The register file and memory both write on the rising clock edge when their respective control signals, RegWr and MemWr, are asserted.

$-$ The extender will zero extend if the ExtOp bit is $0$ and sign extend when the ExtOp bit is $1.$

$-$ The data memory reads asynchronously but has synchronous writes.

$-$ The $"\backslash (=0\backslash )?"$ module will output $1$ if all the input bits are $0,$ and will output $0$ otherwise.

The ALUctr encoding is as follows:

For the following stream of instructions, what does your broken processor actually do$?$ Here are some possible answers.

$-$ Functions correctly

$-$ Incorrect functionality: Indicate the control signals causing this error, and if it implements a different instruction then specify that instruction including the type of operation and registers used $($operation$,$ rs$,$ rt$,$ rd$)$

$-$ Functions correctly only under certain circumstance$($s$)$: Specify the circumstance If there is more than one possibility, list all of them. For simplicity, we have used the actual register numbers rather than names.