Problem #3 [22 pts] Please read section 120 of the AVR Instruction Set Manual and review operation of the STD Z+q, Rr instruction (an indirect store with displacement). (a) List and explain the sequence of microoperations required to implement this instruction on the enhanced AVR datapath (Figure 8.26 in the textbook). Note that this instruction takes two execute cycles (EX1 and EX2) (b) List and explain the control signals and the Register Address Logic (RAL) output for the STD Z+q, Rr instruction. Clearly explain your reasoning. Control signals for the Fetch cycle are given below. IF STD Z+9, Rr EX1 EX2 STD Z+q, Rr EX1 EX2 RAL Output WA WB TA rB 0 0 0 1 1 0 0 1 0 Control Signals MJ MK ML IR en PC en PCh en PCI en NPC en SP_en DEMUX MA MB ALU f MC RF WA RF WB MD ME DM_r DM w MF MG Adder f Inc Dec MH MI XXXX XX 0 0 0 X XX Problem #3 [22 pts] Please read section 120 of the AVR Instruction Set Manual and review operation of the STD Z+q, Rr instruction (an indirect store with displacement). (a) List and explain the sequence of microoperations required to implement this instruction on the enhanced AVR datapath (Figure 8.26 in the textbook). Note that this instruction takes two execute cycles (EX1 and EX2) (b) List and explain the control signals and the Register Address Logic (RAL) output for the STD Z+q, Rr instruction. Clearly explain your reasoning. Control signals for the Fetch cycle are given below. IF STD Z+9, Rr EX1 EX2 STD Z+q, Rr EX1 EX2 RAL Output WA WB TA rB 0 0 0 1 1 0 0 1 0 Control Signals MJ MK ML IR en PC en PCh en PCI en NPC en SP_en DEMUX MA MB ALU f MC RF WA RF WB MD ME DM_r DM w MF MG Adder f Inc Dec MH MI XXXX XX 0 0 0 X XX