Problem $3$: The two$-$way superscalar MIPS implementation below is a reduced cost version of the two$-$way implementation usually shown in class. Red exes show where bypass connections are removed, and a new multiplexor appears in blue $($in the bottom of the EX stage$).$

$($a$)$ Show a code fragment that would stall on this implementation but would not stall on our usual $2-$way superscalar implementation.

$($b$)$ Write a code fragment in which the new mux select signal, labeled A$,$ must be $0$ in one cycle and $1$ in another cycle. Show the value of the select signal in a pipeline execution diagram, leaving the value blank where its value does not matter.