Problem $4(20$ pts$)$: Identify all data dependencies $($RAW$,$ WAR, WAW$)$ in the code below. Assume

a simple MIPS $5-$stage pipeline is used $($register write in the first half of a cycle and register read in the

second half$).$ Find the dependency that causes a data hazard and state whether it requires a stall to be

handled, or can be handled via forwarding. If there is no data hazard, put $"$No$"$ in the last column. Add

extra rows to the table if needed.