Question: Problem 4 (20 points): Write a SystemVerilog module for a mealy FSM to detect the input pattern of 1101 or 1110. The FSM has input

Problem 4 (20 points): Write a SystemVerilog module for a mealy

Problem 4 (20 points): Write a SystemVerilog module for a mealy FSM to detect the input pattern of "1101 "or "1110". The FSM has input ports: clk, reset, a, and output port: q. The FSM reset is asynchronous. (Please refer to the solution to Problem 4 in HW3 for the state transition diagram)

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