Problem $4(30$ Points$)$

We need to extend the pipelined RISC$-$V processor implemented in the lecture slides to handle the RISC$-$V load upper immediate instruction, lui.

a$)$ Update the following Immediate Extend unit to support lui

b$)$ Make the needed changes on the implementation shown in the slide titled: RISC$-$V

Pipelined Processor with Hazard Unit to support the implementation of lui

c$)$ Explain how the additional components you used in part $($b$)$ to implement lui will

affect the RISC$-$V pipelined critical path. Support your answer by recalculating the

$T_{c_p\text{i}\text{p}\text{e}\text{l}\text{i}\text{n}\text{e}\text{d}}$ using the delays listed in the table of the Pipelined Critical Path Example slide.

d$)$ Update the following Control Unit $-$ Instruction Decoder to support lui