Problem 4 (3 points): Instruction set architecture and performance Suppose a new version of the MIPS architecture is proposed, called the MIPS RegMax. The RegMax is similar to the MIPS, but has 256 registers, rather than 32. The three instruction formats for the RegMax are: R-Type: Opcode: 6 bits r rd: 8 bits I-Type: Opcode: 6 bits rs: 8 bits J-Type: rs: 8 bits rt: 8 bits shamt: 0 bits funct: 2 bits rt: 8 bits immediate: 10 bits (a) Describe two ways that RegMax might reduce instruction count relative to the baseline MIPS architecture. (b) Describe three ways RegMax might increase instruction count relative to the baseline MIPS architecture. (c) With the elimination of the shamt field in the R-type instruction format, describe how shift instructions can be implemented in the instruction set. Problem 4 (3 points): Instruction set architecture and performance Suppose a new version of the MIPS architecture is proposed, called the MIPS RegMax. The RegMax is similar to the MIPS, but has 256 registers, rather than 32. The three instruction formats for the RegMax are: R-Type: Opcode: 6 bits r rd: 8 bits I-Type: Opcode: 6 bits rs: 8 bits J-Type: rs: 8 bits rt: 8 bits shamt: 0 bits funct: 2 bits rt: 8 bits immediate: 10 bits (a) Describe two ways that RegMax might reduce instruction count relative to the baseline MIPS architecture. (b) Describe three ways RegMax might increase instruction count relative to the baseline MIPS architecture. (c) With the elimination of the shamt field in the R-type instruction format, describe how shift instructions can be implemented in the instruction set