Problem 4124 points A. Copae the performance of two cache designs for a byte-addressed memory system. The first cache design is a dircct-mapped cacbe (DM) with four blocks, cach block holding onc four-byte word. Tho second cache has the same capacity and block size bu is fully associatve (FA) with a least-recently used replacement policy. (6 points) F the following sequences of memary read accesses to the cache, compare the relative performance of the two caches. Assme that all blocks are invalid initially, and that cach address sequence is repeated a largc mumher of tmes Ignore compulsory misses when caleulating miss rates. All addresses are given in decimal Fully associative: aow a given block to go in any cache entry Compulsory miss: This occurs when a process starts, or restarts, or touches new data Least-recently used: Choose the one unused for the longest time i. (2 points) Memory Accesses: 0,4,0,4, (repeats) The Miss Rate is: DM Miss Rate FA Miss Rate 0% 0% 547% 100% 100% ii. 2 points) Memory Accesses: 8, 12, 16, (repeals) The Miss Rate is: DM Miss Rate 20% FA Miss Ratc 0% 20% 20% 4010 1917% 00% e) iii. (2 points) Memory Accesses: 0,4, 8, 12, 16, 12, 8,4, 0, 4,8, 12. 16, 12, 8,4, The Miss Rate is: DM Miss Rate FA Miss Rate 25% 0% ck 50% 50% 100% 00% B. Fi in the following parts, Rel tht AMAT t Time Miss Rate Miss Penalty. (4 point) i. Assme Hit Time is 1 cycle und the miss penalty is 100 cycles What should be the value of the miss rate to achicve an AMAT of 2 cycles? (1 point) As in (a) but now assume the miss penalty is 800 cycles. What is the miss rate needed to achieve an AMAT of2 cycles (1 point) iu. Assume a two-level cache where the LI hit time is as in (a.' and the hit time in the L2 cache is 2 cycles and the miss penalty is 800 cycles Further assume n L miss rte of Show how you calculate the L2 miss rate to achieve an AMAT of 2 cycles. What is the L2 miss rate you calculated(2 point)