Problem $5$: How Fast Is My Logic...

$[12$ pts$]$ The simplified switch model of NMOS and PMOS transistors we've studied so far model one imperfection: the on resistance of a transistor. In this problem, we study a second imperfection: because of how MOS transistors are constructed, there is a capacitance between the gate and the source. These capacitances, and how fast you can charge them, limit how fast computers $($which contain billions of logic gates$)$ can operate.

For simplicity, we have reduced the complex problem of constructing an equivalent capacitance model, to an inverter gate charging $($or discharging$)$ a capacitor $\backslash ($ C$\_\{\backslash$text $\{$load $\}\}=10\backslash$mathrm$\{$fF$\}\backslash ),$ as shown in the diagram below. One can imagine the load capacitor to be the equivalent capacitance of the logic gates connected to the output of the inverter gate

In this problem, assume that $\backslash ($ V$\_\{$D D$\}=1\backslash$mathrm$\{$~V$\}\backslash ),$ that $\backslash ($ R$\_\{\backslash$mathrm$\{$on$\}\}=4\backslash$mathrm$\{$k$\}\backslash$Omega $\backslash )$ for all transistors.

$($a$)[6$ pts$]$ To start to understand the behavior of the voltage at node OUT $($the output of the driving logic gate$),\backslash ($ v$\_\{\backslash$text $\{$out $\}\}($t$)\backslash ),$ draw equivalent circuits for each of these two cases:

$($i$)$ when A is at logical $\backslash (1\backslash$left$($v$\_\{$A$\}=1\backslash$mathrm$\{$~V$\}\backslash$right$)\backslash ),$ and

$($ii$)$ when A is at logical $\backslash (0\backslash$left$($v$\_\{$A$\}=0\backslash$mathrm$\{$~V$\}\backslash$right$)\backslash )$

Your schematic should show the resistance of the relevant transistors that are turned on in the inverter gate. $($You can omit all components that aren't relevant to understanding $\backslash ($ v$\_\{\backslash$text $\{$out $\}\}\backslash ).)$

$9$

$($b$)[6$pts$]$ For a gate to turn on$,$ the input must reach a certain voltage, called $\backslash ($ V$\_\{\backslash$text $\{$switch $\}\}\backslash )$ of the gate, which causes the output voltage to change. This voltage is close to $\backslash (50\backslash \%\backslash )$ of Vdd$,$ so gate delay is measured as the time the input reaches $\backslash (\backslash$mathrm$\{$Vdd$\}/2\backslash )$ to the time the output reaches this voltage. So when the load capacitance $\backslash ($ C$\_\{\backslash$text $\{$load $\}\}\backslash )$ voltage $\backslash ($ v$\_\{\backslash$text $\{$out $\}\}\backslash )$ is $\backslash (50\backslash \%\backslash )$ of the way to its final value, the gate turns on$.$ Let's further assume that the transistors "turn on$/$off$"$ at this voltage as well $($not completely true, but ok for a first order estimate of delay$).$ For each of the two cases, solve for what happens when A transitions from $0$ to $1,$ and when it transitions from $1$ to $0.$