Problem $7$

For the given assembly program, reverse$-$engineer the microarchitecture of the Tomasulo

pipeline that would execute it as the execution timeline shown. Find the minimum cost solution $($minimum number of reservation station entries, pipeline registers and etc$).$

Things that are known about the microarchitecture:

$$

There are one ADD unit, one MUL unit, and one DIV unit.

$$

The pipeline stages are IF$,$ ID$,($EXE$/$MEM$),$ WB$,$ where the latency of EXE$/$MEM stage

varies among functional units.