Problem $7$:

Given the following latencies for a $5-$stage pipeline:

IF ID EX MEM WB

$200$ ps $300$ ps $100$ ps $250$ ps $150$ ps

a$)$ What is the clock cycle time in a non$-$pipelined processor?

$200$ ps $+300$ ps $+100$ ps $+250$ ps $+150$ ps $=1000$ps

b$)$ What is the clock rate in a non$-$pipelined processor?

Clock rate $=1/$ Clock cycle time $=1/(1000$ ps$)=1$ GHz $($since $1$ GHz $=1/1000$ ps$)$

Clockrate $=1$GHz

c$)$ What is the clock cycle time in a pipelined processor?

pipeline clock cycle $=$ max$($all stage delay$)$

$=$ Max$(200,300,100,250,150,)=300$ps

d$)$ What is the clock rate in a pipelined processor?

Clockrate $=1/300$ps $=3\mathrm{.}33$GHz Clockrate$=3\mathrm{.}33$GHz

e$)$ How long will it take a Load instruction in this pipeline?