Problem Statement: A kitchen timer is a device that allows a countdown timer to be set for a certain number of minutes and seconds, after which the device audibly alerts that the countdown is complete. For the minutes and seconds, the time is stored in two sets of FFs$,$ one that represents the tens digit and another the ones digit. The FFs count in binary from $1001$ to $0000($or $9$ to $0$ in decimal$)$ for the ones digit and from $101$ to $000($or $5$ to $0$ in decimal$)$ for the tens digit. The maximum storable value is $59$ minutes and $59$ seconds.

A square waveform of one cycle per second is required to get the kitchen timer working precisely. If this $1$ Hz square waveform is divided by $60,$ one pulse per minute waveform is obtained. This is the concept on the basis of which a kitchen timer is designed. A simplified conceptual block diagram of a kitchen timer is given in the figure below.

The first divide by $60$ counter changes the incoming $1$ cycle per second square waveform and converts it into $60$ discrete states $($i$.$e$.,$ the first counter divides the incoming pulse into $60$ sections$).$ This counter is called the seconds counter $($as has been illustrated in the figure$)$ because $60$ discrete states of this counter represent seconds. The second divide by $60$ counter once again changes its state after every one minute and comprises $60$ discrete states $($in other words, the second divide by $60$ counter further divides the incoming $1$ cycle per minute pulse into $60$ sections$).$ As this counter is decoded to display minutes, it is called a minutes counter.

A divide by $60$ counter can be implemented by cascading divide by $10$ and divide by $6$ counters $($i$.$e$.,106=60).$ As a result of cascading $($applying one counter's output on a second counter's input$)$ both counters, a divide by $60$ counter can be obtained.

Design a kitchen timer circuit by using synchronous counters, BCD to $7-$segment decoders, and $7-$segment displays. The designed kitchen timer circuit should satisfy the following requirements:

In the circuit, two synchronous counters need to be designed as building blocks: a divide by $10$ counter $($decade count$-$down counter$)$ and a divide by $6$ counter $(5-0$ counter$).$ Also, it will be assumed that a $1$ Hz square waveform is available.

JK flip$-$flops should be used to build the synchronous counters that count the minutes and seconds.

To display the time, a TTL MSI $7447$ BCD to $7-$segment decoder$/$driver and $7$ segment displays should be used in counters.

Seconds and minutes counters are required to show seconds and minutes in a display constructed by $7-$segment displays.

The kitchen timer should have a reset button to reset all counters if needed.

The kitchen timer should have two push buttons to set minute and second outputs. Minutes and seconds count of the kitchen timer can be changed by pressing push buttons in order to adjust the time. If only the minute button is pressed and the timer is not currently counting down, then the currently set time is increased by one minute. If only the second button is pressed and the timer is not currently counting, then the currently set time is increased by one second.

The kitchen timer should have a start button to start counting down. If a time has been set and the start button is pressed, then the timer starts counting down. The timer can only be started by pressing start.

The kitchen timer circuit must have an alarm output to produce a Logic $1$ signal at the end of the required duration.

Hints:

To decode seconds counter, a divide by $10$ counter can be cascaded with a divide by $6$ counter. In this way, a divide by $60$ counter, which decodes $60$ seconds in one minute, can be obtained. As a result of the decoding of the divide by $10$ counter output, the second$\text{'}$s second digit and the decoding of the divide by $6$ counter output, the second$\text{'}$s first digit can be displayed on $7-$segment displays.

As both divide by $10$ and divide by $6$ counters count directly in binary, using a $7$ segment decoder$/$driver with each, two $7-$segment displays can be driven.

Just like the seconds counter, the minutes counter also functions exactly in a similar manner, except that a $1$ cycle per minute square waveform is received on the minutes counter from the seconds counter.

Submission: Project report must be submitted on paper in one stapled packet. Report should contain your complete working circuit with the correct input and output components, clearly labeled in this order:

A state diagram for each synchronous counter and all state transitions clearly labeled.

State table and don't cares for the unused states.

K$-$maps clearly labeled for each of the Flip$-$Flop input equations and output equation and simplified Boolean functions for each one.

A print$-$out of the logic diagram of the digital clock circuit.

Also Proteus file of the complete circuit must be submitted electronically.

I need to submission for logic design