Problem W$11\mathrm{.}6$

Design a "divisible$-$by$-3"$ FSM that accepts a binary number entered one bit at a time, most significant bit first, and indicates with a light if the number entered so far is divisible by $3.$

A$.(1$ pt$)$ Prove mathematically that this FSM can be implemented using three states, each state representing the remainder after the number entered so far is divided by $3.($Hint: a multiple of $3$ can be written as $3n,$ where $n$ is an integer$).$

B$.(1pt)$ Show the state diagram for this FSM$.$

C$.(2$ pts$)$ Implement the circuit with such state assignment that you can eliminate the output logic.