Problem:3 Answer the following questions regarding sequential logic circuits. Assume that the clock is an ideal rectangular wave without skew, and that the gate delay is short enough compared with the clock cycle. (1) Choose one from D flip-flop, JK flip-flop and T flip-flop, and explain how its output is determined by the clock, the inputs and the internal state. (2) Design and depict a circuit ALT, whose output toggles between 0 and 1 every clock cycle as illustrated below. You can use the flip-flop you have chosen in Question (1), and the AND, OR and NOT gates. Clock Output of ALT Problem:3 Answer the following questions regarding sequential logic circuits. Assume that the clock is an ideal rectangular wave without skew, and that the gate delay is short enough compared with the clock cycle. (1) Choose one from D flip-flop, JK flip-flop and T flip-flop, and explain how its output is determined by the clock, the inputs and the internal state. (2) Design and depict a circuit ALT, whose output toggles between 0 and 1 every clock cycle as illustrated below. You can use the flip-flop you have chosen in Question (1), and the AND, OR and NOT gates. Clock Output of ALT